The present invention relates to a method of fabricating a semiconductor device by which a thickness of an oxide film is prevented from being relatively thinned at the boundary between a shallow trench isolation structure and a thick gate oxide film when a dual gate oxide fabrication process is applied to a normal shallow trench isolation structure.
Power devices such as a liquid crystal display (LCD) driver integrated circuits IC (LDI) require both low voltage (LV) operation for driving an associated logic circuit together with high voltage (HV) operation for driving the LCD during operation. Accordingly, associated gate oxide films are commonly formed of the dual-gate type. In addition, the continuous trend toward ever-miniaturized line width requires the use of a shallow trench isolation (STI) process for isolating adjacent circuit components.
However, if the process for fabricating the dual gate oxide film is conducted in the same manner as it is applied to the normal STI structure, excessive numbers of STI recesses in the LV region are created during formation of the dual gate oxide film for the HV region, resulting in compromise of the overall device characteristics.
The reason for this is that since the STI is formed of a CVD oxide film material such as USG or HDP, while, in contrast, a gate oxide film is formed of a thermal oxide film material, a severe dent is created in the boundary between an active region and a field region due to the difference in wet etch rate between the thermal oxide film and CVD oxide film, when the dual gate oxide film is formed by an etching process.
Such a conventional process is explained in greater detail explained with reference to FIGS. 1A through 1C below, which illustrate processes for fabricating a conventional dual gate oxide film.
For the sake of convenience, the processes are explained as being divided into 3 steps as follows. In the drawings, reference symbol xe2x80x9cIxe2x80x9d indicates a first active region in which a thin gate oxide film for LV is formed and reference xe2x80x9cIIxe2x80x9d indicates a second active region in which a thick gate oxide film for HV is formed.
First Step:
As shown in FIG. 1A, a nitride film pattern (not shown) is formed in the first and second active regions I, II of the substrate 10. The silicone substrate 10 is selectively etched to a predetermined thickness by using the pattern as mask so that trench (t) is formed in the field region within the substrate 10. The CVD oxide film of USG or HDP material is formed on the resultant material so that the trench (t) is sufficiently filled. Next, the CVD oxide film is chemically mechanically polished so that the nitride pattern in the first and second active regions I, II may remain and thereafter the nitride film is removed. In this manner, the STI 12 that buries the inside of the trench (t) is formed. Subsequently, CMOS well ion-implantation and channel ion-implantation are performed. The first thermal oxide film 14 for HV is subsequently formed in a thickness of 300 xc3x85 in the active region I, II on the substrate 10.
Second Step:
As shown in FIG. 1B, a photo-resist pattern 16 is formed on the resultant structure so that the first active region I and the surrounding STI 12 may partly be opened. The first thermal oxide film 14 is wet etched using the pattern as a mask and selectively remains only in the HV region II.
Third Step:
As shown in FIG. 1C, the photo-resist pattern 16 is removed and the second thermal oxide film 18 for LV is formed at a thickness of 40 xc3x85 in the first active region I. Thereby, the process for the dual gate oxide film is completed. In this case, when the second thermal oxide film 18 is formed, the first thermal oxide film 14 also grows. However, since the amount of the growth is minor, the resultant effect may be negligible.
As a result, the first active region I is formed therein with a thin gate oxide film of the second thermal oxide film 18 material, which is for LV operation. Also, the second active region II is formed therein with a thick gate oxide film of the first thermal oxide film 14 material, which is for HV operation.
However, if the dual gate oxide film is formed according to the aforementioned process, there is a problem as follows during the formation of device.
When the first thermal oxide film 14 of LV region I is removed by using the photo-resist pattern 16 as a mask, the STI 12, which is indicated by xc3xa2 in FIG. 1B, surrounding the circumference of LV region is recessed together with the first thermal oxide film 14. Accordingly, a dent is generated in the region, that is, in the boundary surface between the active region and the field region. FIG. 2 shows the structure of a device having such defect.
Such a defect phenomenon is caused by the difference in a wet etch rate between the first thermal oxide film 14 being used as a gate oxide film and the CVD oxide film forming the STI 12. For example, in the case that the STI 12 is filled with a HDP material, the depth of the recess is approximately 200 xc3x85 relative to the substrate 10 of the active region. In contrast, in the case that the STI 12 is filled with a USG material, the recess amounts to approximately 1,000 xc3x85 relative to the substrate 10 of the active region, creating a more severe dent in this case.
In the event that the dent is created, poly residue remains in the region that is recessed during etching of the gate poly as a follow up process, or the gate poly surrounds the field region and the active region at the boundary between the field region and the active region. This results in deterioration in the gate oxide film due to the concentration of electric field created in an upward and sideward direction, as well as deterioration in characteristics such as drop in threshold voltage Vth of the resulting transistor during the operation of device, increase in threshold voltage leakage, and decrease in punching margin.
In order to solve those problems, there has been disclosed a process technique by which a dual gate oxide film is formed by using a nitride film as a mask even without the need for removing the thick thermal oxide film in the LV region, while the process of fabricating the dual gate oxide film is applied to a normal STI structure in LDI design.
FIGS. 3A through 3E show in order a method of forming such a dual gate oxide. The method comprises the following five steps. Reference symbol xe2x80x9cIxe2x80x9d indicates a LV region in which a thin gate oxide film is formed, and reference symbol xe2x80x9cIIxe2x80x9d indicates a HV region in which a thick gate oxide film is formed.
First Step:
As shown in FIG. 3A, the STI 102 of the CVD oxide film material that buries the inside of the trench (t) is formed in the field region on the silicone substrate 100 according to the same method as that shown above in FIG. 1A. The buffer oxide film 104 of the thermal oxide film material is subsequently formed in the active regions I, II on the substrate 100 and CMOS well ion-implantation and channel ion-implantation are performed. While the buffer oxide film 104 remains intact, a nitride film 106 is formed on the buffer oxide film 104 including the STI 102. Thereafter, the CVD oxide film 108 of medium temperature oxide (MTO) is formed on the resultant material. Here, the MTO refers to an oxide film that is formed at the temperature of 700 to 800xc2x0 C. The buffer oxide film 104 is formed in a thickness of 100 to 120 xc3x85, the nitride film 106 is formed in a thickness of 90 to 110 xc3x85 and the CVD oxide film 108 is formed in a thickness of 90 to 110 xc3x85.
Second Step:
As shown in FIG. 3B, the CVD oxide film 108 is patterned by a photo-resist pattern 110 so that the first active region I and the surrounding STI 102 may partly be masked. The second active region II and the adjacent CVD oxide film 108 are wet etched using the pattern 110 as a mask.
During the third step shown in FIG. 3C, the photo-resist pattern 110 is removed.
During the fourth step shown in FIG. 3D, the nitride film 106 and the buffer oxide film 104 are in order etched by utilizing a mask of the residual CVD oxide film 108, thereby exposing the surface of the second active region II. At this time, the nitride film 104 is etched by a wet etching method in which phosphoric acid is used as etchant.
The residual CVD oxide film 108 that was used as a mask is simultaneously removed when the buffer oxide film 104 is etched. The first thermal oxide film 112 is then formed at a thickness of 400 to 450 xc3x85 on the exposed surface of the second active region II.
In the fifth step shown in FIG. 3E, the nitride film 106 and the buffer oxide film 104 that remain in the first active region I and the adjacent STI 102 are in order etched, thereby exposing the surface of the first active region I. In this case, since a part of the first oxide film 112 is also consumed during the etching process (particularly, etching of the buffer oxide film), the first thermal oxide film 112 remains only at a thickness of approximately 250 to 350 xc3x85 on the second active region II when the etching process on the residual films are completed. The second thermal oxide film 114 is formed in a thickness of 30 to 50 xc3x85 on the exposed surface of the first active region I, such that the second thermal oxide film 114 is thinner than the first thermal film 112. Thereby, the processes for forming the dual gate oxide film are completed. Here, when the second thermal oxide film 114 is formed, the first thermal oxide film 112 of the second active region II also grows an additional amount. However, since the amount of the growth is minor, the resultant effect is negligible.
As a result, the first active region I is formed therein with a thin gate oxide film of the second thermal film 114 material appropriate for LV, and the second active region II is formed therein with a thick gate oxide film of the first thermal film 112 material appropriate for HV.
In the case that the dual gate oxide film is fabricated according to such a method, dent formation can be prevented at the boundary between the active region and field region because the process of removing the thick thermal oxide film in the LV region is not needed during the formation of the thick gate oxide film in the HV region.
However, during growth of the thick gate oxide film of the first thermal oxide film 112 in the second active region II by using the nitride film 106 as a mask, there is a problem in that the first thermal oxide film 112 experiences relatively less growth at the boundary (indicated by {circle around (b)} in FIG. 3E) between the STI 102 and the active region, as compared to adjacent portions. As a result, the first thermal oxide film 112 is severely thinned at the edge portion of the STI 102. The thicker the gate oxide film, the more rapidly this phenomenon is accelerated. FIG. 4 shows the structure of a device having such a defect. In the drawing, the symbol xe2x80x9clxe2x80x9d indicates the predetermined thickness of the first thermal oxide film 112 and xe2x80x9clxe2x88x92xcex1xe2x80x9d indicates the resulting thickness of the first oxide film 112 in the boundary region as a result of the thinning phenomenon.
The source of the thinning phenomenon is the compressive stress that is concentrated at the sides of the STI 102 that is relatively stiff during the thermal oxidation process. When such thinning phenomenon occurs, the gate oxide film is deteriorated due to the concentration of electric field, in addition, an effective transistor is formed at the center of the active region with channels (the channel of flat TR) and turned-on just after a transistor is first formed at the boundary of the active region and field region with channels (the channel of corner TR) and turned-on. As a result of this effective transistor, a hump phenomenon occurs, by which it appears as if the resulting transistor has two Vth values, which should be avoided.
Accordingly, it is an object of the present invention to provide a semiconductor device fabricating method by which a local oxidation of silicon (LOCOS) process is applied to a normal STI structure so that a trench is formed through a LOCOS oxide film and in which the STI includes a portion of a structure, referred to as a xe2x80x9cbird""s beakxe2x80x9d structure, of the LOCOS oxide film so that a side portion of the resulting STI structure includes a slanted structure, and, at the same time, the silicon substrate has a crystal structure (1, 1, 1) at an edge part of an active region that contacts the STI. As a result, thinning of the gate oxide film at an edge portion of STI is mitigated and/or eliminated by relative easing of the compressive stress that would otherwise be concentrated at a side portion of STI during growth of the gate oxide film for HV.
In order to achieve the above object, according to one aspect of the present invention, the semiconductor device fabricating method according to the present invention comprises the steps of: forming a deposition structure of pad oxide film/nitride film/oxide film on a semiconductor substrate so that a field region is exposed; performing an oxidation process using the resultant structure as a mask so that a LOCOS oxide film including a lateral extension, for example an angular bird""s beak extension, is formed in the field region; etching the silicon substrate and the LOCOS oxide film to a predetermined thickness using the resultant structure as a mask so that a trench is formed in the field region; forming a CVD oxide film on the resultant structure so that the trench is sufficiently filled; forming a STI of oxide film material including the lateral extension in the field region by processing the CVD oxide film by a CMP process so that the nitride film remains in a predetermined thickness on the pad oxide film; removing the remained nitride film and the pad oxide film so that the first and second active regions are exposed; performing a CMOS-well ion-implantation process and a channel ion implantation process; performing a nitride film deposition process and a following etching process so that a nitride film remaining in the first active region and the second active region is exposed; forming a first thermal oxide film for a gate oxide film in the second active region by using the remaining nitride film as a mask; removing the remaining nitride film in the first active region; and forming in the first active region a second thermal oxide film for a gate oxide film that is thinner in thickness than the first oxide film.
According to another aspect of the present invention, the semiconductor device fabricating method according to the present invention, comprises the steps of: forming a deposition structure of pad oxide film/nitride film/oxide film on a semiconductor substrate so that a field region is exposed; performing an oxidation process using the resultant structure as a mask so that a LOCOS oxide film including a lateral extensions, for example an angular bird""s beak-shaped extension, is formed at the field region; etching the silicon substrate and the LOCOS oxide film to a predetermined thickness using the resultant structure as a mask so that a trench is formed at the field region; forming a CVD oxide film on the resultant structure so that the trench is sufficiently filled; forming a STI of oxide film material including the lateral extension in the field region by processing the CVD oxide film by a CMP process so that the nitride film remains in a predetermined thickness on the pad oxide film; removing the remaining nitride film and the pad oxide film so that the first and second active regions are exposed; performing a CMOS-well ion-implantation process and a channel ion implantation process; forming a first thermal oxide film for a gate oxide film in the first active region and the second active region; removing the first thermal oxide film in the first active region; and forming, in the first active region, a second thermal oxide film for a gate oxide film thinner than the first thermal oxide film.
The first active region preferably indicates a low voltage (LV) region and the second active region indicates a high voltage (HV) region.
According to the processes of the present invention, since the side portions of the STI structure is formed with a slanted angular extension (for instance, a bird""s beak shape), and not a conventional vertical shape, and since an etching process is performed so that a portion of the bird""s beak is also etched when the remaining nitride film and the pad oxide film in the first and second active regions are removed, the silicon substrate has the crystal structure (1, 1, 1) at the edge portions of the first and second active regions that are in contact with the STI.
As a result, compressive stress that otherwise would be concentrated at the side portion of the STI during the oxidation process can be eased relative to the conventional technique, thereby preventing the thickness of the gate oxide film for HV from being relatively thinned at the edge portion of STI.